High performance microprocessors, may use out-of-order instruction execution rather than conventional sequential execution that requires all instructions to execute in sequential order. As such, if the next sequential instruction does not have all of its operands in a valid state, the instruction pipeline stalls until the operands become valid. In contrast, an out-of-order microprocessor executes instructions as soon as its operands become valid, independent of the original instruction sequence. Consequently, as these high performance microprocessors execute out-of-order instructions, the microprocessors generate numerous temporary register results. The temporary values are stored together with permanent values in register files. The temporary values become permanent values when the corresponding instructions are retired. An instruction is retired when the temporary result becomes the new state of the microprocessor.
To ensure that each instruction is provided with the correct operand value, each logical register number referenced in the instruction is mapped to a physical register. Each time a new value is placed in a logical register, the logical register is assigned to a new physical register. As a result, each physical register holds a single permanent or temporary value. In this manner, data dependency issues commonly associated with out-of-order instruction execution are avoided.
Since these high performance microprocessors perform out-of-order execution, an instruction can change its register value before all of the prior instructions complete. However, if any of the prior instructions cause an exception, all of the sequential instructions prior to the time the exception occurred are flushed. As a result, the registers allocated to the instructions being flushed become available for allocation to newly decoded instructions.
Typically, a free register list contains just enough capacity to track the maximum allowable number of free physical registers. When physical registers are assigned to an instruction a vacancy is created in the free register list that is immediately filled with a pointer to the physical register that will become free once that instruction retires. Consequently, the typical free register list does not store pointers to physical registers that were recently assigned to an incoming instruction. Hence, when it becomes necessary to process a flush, it is the contents of the free register list that must be restored to a prior state, not the registers in the physical register file. Unfortunately, this method is burdensome and time consuming because it requires at least two additional operations to restore a free physical register list to its previous state.